Abstract
Avalanche transistor switching at extreme currents is studied under conditions in which the charge of the excess carriers drastically rebuilds the collector field domain, causing fast switching and a low residual voltage across the switched-on device. The dynamic numerical model includes carrier diffusion and considers different dependencies of the velocities and ionization rates for the electrons and holes in the electric field. These dependences determine the principal difference in the switching process between n/sup +/-p-n/sub 0/-n/sup +/ and p/sup +/-n-p/sub 0/-p/sup +/ structures. Reasonably good agreement is found between the simulated and measured temporal dependences of the collector current and voltage drop across the device for a particular type of avalanche transistor. Certain differences in the switching delay can partly be attributed to limitations in the one-dimensional (1-D) approach. It is now certain that collector domain reconstruction defines the transient in a n/sup +/-p-n/sub 0/-n/sup +/ transistor at high currents, but is not very pronounced in a p/sup +/-n-p/sub 0/-p/sup +/ transistor. Some nontrivial features of the device operation are found, depending on the semiconductor structure. In particular, it is shown that the thickness of the low-doped collector region affects mainly the switching delay, and does not significantly effect the current rise time.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.