PROMPT3-a cell-based transistor sizing program using heuristic and simulated annealing algorithms

Abstract

PROMPT3, an innovative cell-based transistor sizing program, automatically sizes logic cells to meet the desired timing goal and to minimize the total active area. The optimization includes both heuristic and simulated annealing algorithms. To satisfy the timing specification, PROMPT3 iteratively uses a sensitivity-based heuristic algorithm to reduce gate delays and to derive a performance-optimized circuit configuration. Using this initial circuit configuration, PROMPT3 then applies a simulated annealing algorithm to minimize active chip area while maintaining the specified timing constraints. Preliminary results indicate that the speed of the circuit can be doubled. Using only the heuristic algorithm increases the total active chip area by 25%. However, this increase can be reduced to 15% after applying the simulated annealing algorithm. The authors discuss the algorithms and preliminary test results of PROMPT3