Abstract

The research and commercialization of SiC based power device have been burgeoning over the last decade worldwide, which is bringing about an increasing demand on lost-cost and low-defect SiC wafers. To meet this challenge, we have been continuously making efforts on improving the crystal growth and wafer processing techniques. Now, the mass-production of high quality 4-inch, 6-inch n-type and semi-insulating SiC wafers has been realized. Statistically, the micropipe density is lower than 0.5 cm-2. The resistivity of the wafers is lower than 0.02 Ω·cm and up to 108 Ω·cm for n-type and semi-insulating SiC single crystals, respectively. A state of the art processing technique has been developed to control wafer deformation and thickness within the desired values for subsequent epitaxy. The total defect number of the epitaxial layers grown on the "epi-ready" 4-inch SiC wafer is 63, and the usable area is 97.6%, indicating the high quality of our SiC substrates.

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