Programmed PWM of 5- and 7-Level Multilevel Inverters to Meet 5% Voltage Distortion Limit

Abstract

Multilevel inverters have gradually found commercial application as motor drives, solar inverters, etc. Output voltage distortion and overall switching losses, which are related via the frequencies at which their active devices are switched, are the main performance metrics of these converters. As wide-bandgap semiconductor devices become more common, their comparatively lower switching losses motivates the study of control schemes that utilize somewhat higher device switching frequencies to achieve lower waveform distortion i.e., programmed PWM. This paper describes a continued study of the minimal THD that 5-level symmetric and asymmetric multilevel inverters (MLIs), and also 7-level symmetric and asymmetric MLIs, can achieve with various numbers of switching angles/output voltage waveform transitions. Then key computed results were verified experimentally. In particular, the results indicate that programmed PWM with no more than 16, 14, 13 and 13 transitions, respectively, per quarter cycle will enable symmetric and asymmetric 5-level MLIs, and symmetric and asymmetric 7-level MLIs, to achieve output voltage distortion (THD50) of less than 5%.