Programmable-Gain Capacitive Feedback TIA for Low-Noise Applications in CMOS

Abstract

The work reports on the design of an area-efficient programmable-gain low-noise CMOS transimpedance amplifier suitable for entry-level optical time-domain reflectometers. The approach is based on a modified capacitive feedback topology with the gain variation implemented using a simultaneous adjustment of one of the feedback capacitors and the biasing impedance for the input stage. A more accurate design methodology is proposed including explicit modeling of the biasing circuits and modifications of the reference design are suggested including PMOS-based biasing and DC current elimination. Five different gain modes are implemented using standard 180 nm CMOS process with the base 10 kΩ configuration demonstrating the bandwidth of 1.1 GHz and average input-referred noise current density below $1.8{\text{pA}}/\sqrt {{{\text{H}}_{\text{Z}}}} $ in the presence of a 0.7 pF total input capacitance. With the capacitive feedback structure addressing noise problem of conventional feed-forward or resistive feedback designs, the proposed TIA shows a power consumption around 21 mW in all the configurations while running from 1.8 V power supply.