Programmable Platform Characterization for System Level Performance Analysis

Abstract

It is customary to begin a discussion of Electronic System Level (ESL) design by stating at least one of the following observations [7]: • Time-to-market is a major influence on the design of most electronic systems; • Design complexity has outpaced designer productivity; • Verification effort now dominates design effort; • Custom design costs too much to be practical for most designs; • Register Transfer Level (RTL) design methods will not scale to address the design complexity; • Designers must work at higher levels of design abstraction to overcome design complexity; • Design re-use will be necessary to overcome design complexity. Figure 1 presents a graph relating design complexity to designer productivity with both RTL and ESL design methods. Today, most designers work with RTL design tools and languages. They find themselves in the ‘design gap’ where the system they are trying to create exceeds the capabilities of their design environment. This is not to say that the design gap cannot be crossed. On the contrary, the gap can be overcome with existing design methods but only at a significantly increased cost (both financially [5], [6] and in designer effort). Existing RTL design methods will continue to be employed until the additional cost of design overwhelms the