Abstract
The architecture for an advanced, modular, all-digital programmable receiver capable of processing bandwidth-efficient digital modulation schemes at data rates well in excess of 100 Mb/s is described. The receiver is designed around a digital, parallel processing architecture to support high throughput rates while being adaptable to both continuous and burst communication systems. Based on the combined use of GaAs and CMOS technologies, a digital architecture that provides significant processing flexibility is presented. The programming of all critical receiver functions and attributes is supported through this architecture. The general concept is based on a set of high-speed programmable and reconfigurable building blocks that provide the user complete control of the demodulation, tracking, and data-processing functions. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
