Program realization of simulation tools of low-density codecs: effective architecture of a decoder for massive parallel computations on graphic processors

Abstract

The article deals with the peculiarities of modeling the characteristics of low-density parity-check codes (LDPC) in terms of their decoding. When decoding low-density parity-check codes in various communication standards, the iterative belief propagation algorithm (BP) and its various modifications - Pearl’s algorithm, sum-of-products algorithm - are widely used. In the article, special attention is given to this algorithm. The BP algorithm is a message-passing algorithm on a graphical model and consists of two basic messaging procedures between the nodes in the Tanner graph for LDPC code. The issues of constructing an effective architecture for an iterative decoder operating on the belief propagation algorithm in a heterogeneous system with massively parallel computing on a graphics processing unit are considered. It is shown that the use of the GPU allows to achieve a significant gain in decoding time with a sufficient size of the test matrix (a sufficient number of code and test nodes), obtained due to the parallelism of the architecture. Expressions for calculation of the size of the “working group” are given. The benefit of using a modified decoder architecture is estimated.