Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage

Abstract

Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but the flip flop with the double-edge sensor amplifier (DETSAFF). Another common technique for dynamic energy consumption reduced when the device is idle is the clock gating. In this document. Sleep is used to reduce the power of the leakage Here are the following: High threshold voltages sleep transistors are used. Among the supply voltage and VDD the sleep pMOS transistor and the pull-up system and between the network and the ground GND a sleep NMOs Transistor is located. With sleep transistors, CG-SAFF can save up to 30% of its power during zero input switching operation. For different sequential device architecture, the proposed flip-flop may be used.