Abstract
The paper summarizes the design, the fabrication and test of a chip for the silicon drift detector experiment, part of the A Large Ion Collider Experiment (ALICE) at CERN. The chip performs data reduction via bidimensional compression and packing for the readout chain of the experiment. The chip interfaces with front-end electronics and with the counting room. It is synchronized with a 40 MHz system master clock and configured via a serial signal. The work presents the tests that were performed to characterize the chip and it exploits the final yield of 89% over 700 fabricated chips. The whole tests were performed in laboratory and the chip was also tested in a test beam at CERN in November 2004.
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