Producing stress- and fault-free epitaxial silicon over buried antimony layers

Abstract

Dislocation loops and stacking faults within and upon epitaxial silicon were eliminated in a BiCMOS production line by a three level attack. This success was accomplished by modifications to: the initial oxidation cycle leading to well-gettered substrate, the buried antimony diffusion cycle and the epitaxial deposition process steps. The lead indicator of epitaxial silicon structural issues was and is poor electrical performance of isolated N-channel transistors. The root cause of the dislocation loops was determined to be antimony buried layer implant induced residual lattice strain in the silicon substrate. The source of the stacking faults was isolated to surface residue on antimony buried layers after the diffusion cycle. The lattice strain is relieved through judicious antimony buried layer diffusion cycling. The stacking faults are eliminated by a change in the wafer cleaning methods before epitaxy. The changes detailed in this paper have lead to epitaxial silicon quality enhancement with concomitant improvements in isolated N-channel transistor performance. This paper presents the work leading up to beneficial modifications to the initial oxidation cycle, the antimony buried layer diffusion process and the epitaxial deposition process modules. The presence of epitaxial silicon flaws is indicated by electrical tests (breakdown voltage test and current leakage test) and surface morphology. Schematics and graphs of the electrical test structure, electrical data and SEM images detailing the problem are presented.