Abstract
Students in intermediate hardware design courses face a number of difficulties while designing and implementing complex circuits using Hardware Description Languages (HDLs) and Field-Programmable Gate Arrays (FPGAs). One of the major reasons for this difficulty is that only a subset of HDLs can be synthesized and HDLs differ significantly from the usual sequential high-level programming languages. Further, visualizing the concurrency offered by HDLs is challenging. In this paper, we describe ProcGen, a tool which we have designed and implemented for students to design complex circuits in a hierarchical manner through visualisation of signal propagation. The tool allows easy export and import of designed circuit in VHDL. This paper discusses the architecture and features of ProcGen.
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