Processing of Poly-SiC Substrates with Large Grains for Wafer-Bonding

Abstract

The transfer by wafer-bonding of single-crystalline SiC thin films to a polycrystalline SiC support to obtain a “quasi-wafer” is an attractive way for lowering the cost of silicon carbide wafers. Such a process needs high quality polycrystalline substrates, with controlled and high-level bulk properties (thermal conductivity, electrical resistivity) and with very low surface roughness and surface bowing. Currently, polycrystalline SiC wafers which are available are siliconized SiC or CVD processed SiC wafers. Siliconized ceramic wafers are very heterogeneous (mixture of 3C, 6H, 15R and silicon), while CVD ones are of better quality (homogeneous and textured 3C). However neither the siliconized SiC nor the CVD SiC can be CMP polished with low roughness over large dimension. In this paper, wafers with large and textured grains (> 1cm) are processed and characterized. The polishing of such structures is studied and optimized to obtain low surface roughness. To meet these requirements high temperature processes used for single crystal growth were selected. Structural investigations performed on the grown ingots showed an important influence of the used seed since no preferential crystallographic orientation was observed during the growth. The final polishing quality was of high level but step heights were observed between grains.