Abstract
Process window simulation results are implemented into a yield drop case induced by ILD contact module process shift. Signatures of blind voltage contrast and ILD thickness variation coincide with failure map of wafer sort. Lower down the edge pressure of ILD CMP and increase the O2 flow ratio in BPSG SACVD process can well-control the ILD CMP thickness variation within 500A, and get more uniform dopant distribution in ILD layer. Yield is back to normal after processes optimization.
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