Process variation aware dynamic power management in multicore systems with extended range voltage/frequency scaling

Abstract

Emerging multicore processors are increasingly power constrained and plagued by design uncertainty due to process variations. This paper proposes a novel framework that enables runtime core selection, thread-to-core mapping, and extended range dynamic voltage frequency scaling (DVFS) operating under near-threshold computing (NTC), nominal, and turbo-boost (TB) conditions. Our framework leverages the process variation profile information of each core together with dark-silicon constraints in chip multiprocessors (CMPs) to select cores, map applications, and compute the optimal voltage and frequency operating points of each core to (i) minimize energy under throughput constraints or (ii) maximize throughput under power constraints. Our experimental results motivate the need for extended range DVFS and consideration of process variation information. Our framework that supports extended range DVFS results in 15% energy savings and 14.6% higher throughput compared to a framework that uses nominal mode only DVFS. Furthermore, the process-variation awareness of our framework results in 3.7% energy savings and 11.9% improvement in throughput over prior work that does not leverage process-variation information during dynamic power management.