Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices.

Yinhua Cui,Sung Gyu Pyo,Yuan Gao,Jeong Yeul Jeong

doi:10.3390/mi11010032

Abstract

This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etching 200 Å IMP Ti (ion metal plasma titanium) 200 Å CVD TiN (titanium nitride deposited by chemical vapor deposition) 2 × 50 Å. The resistivities of the glue layer and barrier, i.e., IMP Ti and CVD TiN, were 73 and 280 μΩ·cm, respectively, and the bottom coverages were 57% and 80%, respectively, at a 3.2:1 aspect ratio (A/R). The specific resistance of the tungsten film was approximately 11.5 μΩ·cm, and it was confirmed that the via filling could be performed smoothly. RF etching and IMP Ti should be at least 200 Å each, and CVD TiN can be performed satisfactorily with the existing 2 × 50 Å process. Tungsten deposition showed no difference in the via resistance with deposition temperature and SiH4 reduction time. When the barrier scheme of RF etching 200 Å IMP Ti 200 ÅCVD TiN 2 × 50 Å was applied, the via resistance was less than 20 Ω, even with a side misalignment of 0.05 μm and line-end misalignment of ~0.1 μm.

Highlights

With increased integration of logic devices, the number of metal wiring layers in multilevel metallization (MLM) has increased from 5 layers to 6–12 layers, and the wiring width has become low [1,2]
The hole sizes of vias used to connect the wiring layers have decreased, whereas the thickness of the inter-metal dielectric (IMD) [3], which determines the height of the vias, has hardly changed, resulting in a sharp increase in the aspect ratio (A/R; via height/via hole size) [4,5]
W plugs are applied to the via used in MLM structures of logic devices, and it is reasonable to apply ionized metal plasma physical vapor deposition (IMP PVD) Ti and titanium nitride deposited by chemical vapor deposition (CVD TiN) structures to logic devices [13,14]

Summary

Introduction

With increased integration of logic devices, the number of metal wiring layers in multilevel metallization (MLM) has increased from 5 layers to 6–12 layers, and the wiring width has become low [1,2]. The hole sizes of vias used to connect the wiring layers have decreased, whereas the thickness of the inter-metal dielectric (IMD) [3], which determines the height of the vias, has hardly changed, resulting in a sharp increase in the aspect ratio (A/R; via height/via hole size) [4,5]. In this situation, the via has reached its filling limit with the conventional Al reflow or 2-step Al deposition process [6,7]. W plugs are applied to the via used in MLM structures of logic devices, and it is reasonable to apply ionized metal plasma physical vapor deposition (IMP PVD) Ti and titanium nitride deposited by chemical vapor deposition (CVD TiN) structures to logic devices [13,14]

Methods

Results

Conclusion