Process Induced Wafer Warpage Optimization for Multi-chip Integration on Wafer Level Molded Wafer

Abstract

In this paper, the demonstration of test vehicle by two kinds of process flows noted as first and last, which integrate chips on mold-based, Cu via wafer with glass carriers, are presented. Their warpage behavior during wafer-form integration will be experimentally and numerically evaluated, and also compared with wafer warpages of 2.5D assembly which applied Si interposer with TSV (through Si via). The C4-first flow is to attaching chips on wafers where the C4 bumps have been completed between mold layer and glass carrier. This flow is similar to 2.5D manufacturing process that the Si interposer was temporarily bonded on a carrier which can suppress the interposer warpage variation during reflow process. The temporary glue is required to protect the C4 bumps during chip on wafer procedures. In regarding to the cycle time and cost, the flow to complete C4 after chips attaching will be further studied. The processed induced u-bump (micro-bump) and u-pad (micro-pad) shift post jointing are observed to be larger than that in 2.5D flow. In the manufacturing process of molded wafer, the high CTE glass carriers are used to reduce CTE mismatch between molding compound and carrier. The significant wafer warpage changing from concave to convex shape was observed after chips attaching on the wafer. And the warpage will be further increased after underfilling and molding processes. To well predict and address the warpage trend, the finite element analyses are carried out to understand the process-induced warpage behaviors, and thus to select better material and process parameter. The key parameters affecting wafer warpages like material properties of molding compound, glass carrier and top-mold thickness are determined by finite element simulation. In light of the handing procedure of wafer form assembling equipment, the preferred wafer warpage shape is determined by experimental results. Finally, the test vehicle have been assembled with substrate as well. The chip module warpage in 2.5D structure is about double than that with molding interposer at 230°C and reversed direction in a convex shape, which is different from molding chip module.