Process Impact and Design Optimization on the Soft Yield of 25nm FinFET SRAM Cells

Abstract

A simulation methodology to correlate process variations to the soft yield of 6-T FinFET SRAM cells is demonstrated. By using the TCAD tool which is calibrated to the recently published 25nm FinFET technology, process impacts on the device electrical characteristics are simulated and stored in behavioral models. Circuit simulations can then be carried out to calculate the read/write noise margin. Employing the linear function approximation of the noise margin with respect to the six individual process variation parameters in sigma, one can analytically solve the yield when noise margin drops to zero. The calculation results show that instead of Vt variation, parasitic resistance fluctuation dominates fails at high bias voltages. A simple design optimization guideline is also demonstrated to reduce Vmin of the given technology (to 0.5V in this work). This methodology can serve as useful guidelines for both process development and device design.