Process Definition for Obtaining Ultra-Thin Silicon Oxides Using Full-Wafer Electrical and Optical Measurements

Abstract

ABSTRACTThe objective of this research was to establish a new baseline process for obtaining ultra-thin silicon-oxide gate material in a prototype vertical furnace. Of particular concern was the optimization of a process sequence whereby unpatterned 150 mm diameter wafers ‘see’ the same processing steps prior to gate oxidation as patterned device wafers ‘see’. The figures-of-merit for evaluating process optimization include: i) full-wafer current-voltage (I-V) maps using Hg-gate capacitors; ii) the variation in the current or current density at a given bias voltage, extracted from an I-V map; iii) the variation in electrical oxide thickness that is extracted from full-wafer capacitance-voltage measurements using Hg-gate capacitors; and iv) the variation in optical oxide thickness that is extracted from full-wafer spectroscopic ellipsometry measurements. The results from this research demonstrate that: i) the addition of 1% O2 to the usual N2 gas during the ramp-up cycle in the vertical furnace is necessary to achieve acceptable across-the-wafer oxide-thickness uniformity as determined from both electrical and optical figures-of-merit; and ii) a full-wafer response surface of the current at a given bias voltage is a powerful finger print for process development when the question of variation in as-grown silicon-oxide thickness is at issue.