Process compilation of thin film microdevices

Abstract

This paper describes a systematic method for the automatic generation of fabrication processes of thin film devices. The method uses a partially ordered set (poset) representation of device topology describing the order between its various components in the form of a directed acyclic graph. The sequence in which these components are fabricated is determined from the poset linear extensions, and the component sequence is expanded into a corresponding process flow. The graph-theoretic synthesis method is powerful enough to establish existence and multiplicity of flows thus creating a design space D suitable for optimization. The cardinality /spl par/D/spl par/ for a device with N components is large with a worst case /spl par/D/spl par//spl les/(N-1)! yielding in general a combinatorial explosion of solutions. The number of solutions is controlled through a priori estimates of /spl par/D/spl par/ and condensation of the device graph. The method has been implemented in the computer program MISTIC (Michigan Synthesis Tools for Integrated Circuits) which calculates specific process parameters using an internal database of process modules and materials. Currently, MISTIC includes process modules for deposition, lithography, etching, ion implantation, coupled simultaneous diffusions, and reactive growth. The compilation procedure was applied to several device structures. For a double metal twin-well BiCMOS structure, the compiler generated 168 complete process flows.