Process challenges in low-k wafer dicing

Abstract

Rapid developments in semiconductor industry and the need to maintain interconnect performance as feature sizes shrink are driving a transition to low dielectric constant (k) materials. The very different chemistries and materials properties of low-k dielectric materials may impose novel challenges to wafer/chip manufacturing and packaging processes. Process integration thus becomes more difficult due to the profound changes in properties compared with traditional dielectric materials. Dicing (or sawing) is the first step in the packaging process and its quality can have a significant impact on yields, as well as on device reliability. This paper describes dicing of eight types of Spin-On and CVD low-k wafers. Effects of various blades and dicing process parameters, as well as their combined effect on quality and yield, are discussed. In addition, the effect of cut depth is also examined. Various problems encountered in low-k wafer dicing are presented, and considerations and potential solutions for overcoming these quality obstacles in low-k wafer dicing are discussed. The study shows that the optimized dicing processes must be based on the actual low-k materials, wafer structures and process history of the low-k wafers.