Abstract
High-voltage MOS devices and NMOS logic circuits have been integrated on the same chip by using a silicon-gate isoplanar process that is compatible with present NMOS-LSI technology. The electrical characteristics of a high-voltage MOS device are modeled and characterized in terms of channel length, drift-layer length, drift-layer ion dose, and extended-source field-plate effect. The device structure and the process parameters are optimized to obtain maximum drain saturation current with a low on-resistance and a drain breakdown of 1000 volts. The optimized high-voltage MOS device can perform at a saturation drain current as high as 84 mA with on-resistance as low as 300 Ω within an area of 520 µm × 1320 µm while maintaining a drain breakdown of 1000 volts and drain leakage current less than 30 nA.
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