Abstract
In a recent human body model (HBM) test for non-wired pins of large-scale integrated circuits (LSIs), the LSIs have failed at lower voltage in comparison with the test for wired pins. The failure voltage agreed with the sparking voltage between the non-wired and the adjacent pins. A transient response simulation with a sparking gap showed that the low failure voltage was caused by the low parasitic capacitance on the nodes of non-wired pins. Although these data indicate the electrostatic discharge (ESD) sensitivity of LSIs, the conventional HBM tester could not control the low capacitance. We conclude that the charged device model (CDM) test with variable capacitance or the machine model (MM) test with low capacitance should be carried out besides the HBM test. Application of these data gives us a method to protect quarter-micron LSIs from ESD troubles.
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