Abstract
Extreme ultraviolet (EUV) double patterning (DP) with a numeric aperture (NA) of 0.33 can be introduced for the critical via layers at 3nm logic node. The minimum center to center (C2C) distance of a via pattern may form bridging defects even adopting EUV DP. The implemented via process, pattern shifts induced by EUV illuminator, overlay capability and OPC strategies may lead to bridging defects in EUV DP process. This paper will put forth a compact model to detect potential bridging hotspots and predict the corresponding probability of failure considering aforementioned process variations. The feasible design, patterning solutions, and process parameters can be optimized and compensated quantitatively to avoid design updates and mask rebuild.
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