Privacy preserving computations accelerated using FPGA overlays

Abstract

Secure Function Evaluation (SFE) has recently received considerable attention due to the massive collection and mining of personal data over the Internet, but remains impractical due to its large computational cost. Garbled Circuits (GC) is a protocol for implementing SFE which can evaluate any function that can be expressed as a Boolean circuit and obtain the result while keeping each party's input private. Recent advances have led to a surge of garbled circuits implementations and applications in software to secure evaluation of a variety of different tasks. Due to the high computational complexity in garbled circuits, these implementations are inefficient and therefore GC is not widely used, especially for large problems. This research investigates, implements and evaluates secure computation generation using a heterogeneous computing platform featuring FPGAs. Unlike traditional FPGA design, overlay architecture on FPGAs is adopted since the SFE problem is too large to map to a single FPGA. The system leverages hardware acceleration to tackle the scalability and efficiency challenges inherent in SFE. To that end, we designed and implemented a generic, reconfigurable architecture as a coarse-grained FPGA overlay. On the host side, tools include SFE problem generator, parser and automatic host code generation tool are provided. Compared with tailored approaches that are tied to the execution of a specific SFE structure, and require full reprogramming of an FPGA with each new execution, our design allows re-purposing an FPGA to evaluate different SFE tasks without the need for reprogramming, and fully explores the parallelism for any GC problem. Our system demonstrates significant speedup compared with existing software platforms.