Abstract
The paper defines an algorithm for generating two-bit dithered discrete Fourier basis functions (DDFBF) used in a Stochastic Digital Discrete Fourier Transformation (SDDFT) processor. Based on the theoretical criterion of upper limit precision of norm and orthogonality, the orthonormality of DFT with 32 harmonics is explored by simulation and experimentally. The experiment was detailed and comprehensive, both for norm and for both types of orthogonality. It is performed in 236,8 million points in each of three variants of orthonormality. The matching of theoretical and experimental precision is very acceptable and it can be said with great confidence that the proposed algorithm for generating DDFBF is correct. The DDFBF approach plays a key role in electricity measurement, which is emphasized in the paper.
Highlights
Orthogonal transformations have great importance in measurement and signal processing, and the oldest and most widely used is Fourier transformation
The paper defines an algorithm for generating two-bit dithered discrete Fourier basis functions (DDFBF) used in a Stochastic Digital Discrete Fourier Transformation (SDDFT) processor
Recent developments in the application of diskretne Furijeove transformacije (DFT) in power and energy measurements in the electricity distribution (ED) network have led to the realization of a dedicated stochastic digital DFT (SDDFT) processor whose optimal version is a two-bit SDDFT processor (Author3 et al 2018)
Summary
Orthogonal transformations have great importance in measurement and signal processing, and the oldest and most widely used is Fourier transformation. Recent developments in the application of DFT in power and energy measurements in the electricity distribution (ED) network have led to the realization of a dedicated stochastic digital DFT (SDDFT) processor whose optimal version is a two-bit SDDFT processor (Author et al 2018). The key operation, MAC (Multiply and Accumulate), is performed on simple hardware - the multipliers consist of 4 twoinput "and" circuits and 2 two-input "or" circuits, while the corresponding set of up/down counters execute accumulations. The simple structure of the hardware for performing a two-bit MAC operation, especially if applied in the FPGA implementation of the SDDFT processor, allows high parallelization of DFT calculations and achieving high processing speeds of the analyzed signal. Twobit stochastic additive A/D conversion (SAADC) allows significantly simpler parallel measurements (Author et al 2019)
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