Primary Operation of R/W Gate for Bloch Line Memory Devices

Abstract

Studies of the writing and reading ports of Bloch line (BL) memories were conducted. Previously proposed writing ports had to perform complex manipulations in order to produce stable BL pairs. In order to simplify the write process, we developed a new write process in which a Bloch point merely has to be injected to obtain a stable BL pair. Also, the conditions for domain chopping in BL-bubble conversion, the basic process in read operations, were optimized, and the chip-to-chip variation in the covertible range was reduced. These studies made possible improvements in I/O functions.