Pre-silicon validation of on-die decoupling capacitors in high speed microprocessors

Abstract

Power Supply Noise (PSN) is the switching noise that causes power supply voltage fluctuations. PSN can couple to the evaluation nodes of a circuit, causing functional errors and physical damage. For an under-damped low-loss network, this can manifest itself in the form of a slowly decaying transient noise or a potentially more dangerous resonant noise. As power supply voltage and threshold voltage continue to scale down in nanometer technology, noise margins decrease as well, rendering the control of PSN critical in determining the performance and reliability of high speed VLSI circuits. High Frequency Ldi/dt induced PSN can often be combated with placement of small on-die decoupling capacitors (DCAP) [1]. While there exist many solutions for placement and analysis of DCAP in ASIC and SoC designs [2][3][4], there has so far been no formal algorithm for speedy validation of DCAP placement in a pre-silicon custom design. This paper seeks to describe such an algorithm showing a 92x improvement in runtime when compared with a brute force approach.