Presilicon modeling: challenges in the late CMOS era

Abstract

IEEE Micro editor in chief Pradip Bose writes that in a future of integrated microarchitectures, high-end, server-class microprocessor chips will begin to look like system-on-chip designs with multiple processor cores, special-purpose accelerators invoked on demand, and a scalable on-chip interconnection network, among other on-chip heterogeneous elements. The resulting presilicon modeling challenges in the setting of this late CMOS design era are quite mind-boggling.