Preparation of Transmission Electron Microscopy Samples from Silicon Integrated Circuits

Abstract

A new preparation technique for transmission electron microscopy samples has been developed which allows an individual device within a silicon integrated circuit to be thinned.Typical devices within present silicon integrated circuits are located in the top few microns of a silicon chip, Fig. 1, and have lateral dimensions on the order of a fraction of a millimeter. Sample preparation for electron microscopy is usually accomplished by jet-etching the bottom side of the wafer, directly under the device of interest; thickness is estimated by the color of transmitted light. It is extremely difficult to ensure that the sample will be thinned in exactly the area of interest since the jet is incident on the bottom side of the sample while the device is on the top side, making exact alignment difficult; the jet is large compared to transistor dimensions; the presence of differently doped regions leads to non-uniform thinning.