Abstract
Although scaling will continue for couple of decades but device geometries reaches to atomic size and limitation of quantum mechanical physical boundaries. To address these problems there is need of innovation in material science & engineering, device structure, and new nano devices based on different principle of physics. So TiO2 thin films have been grown on well clean N-type silicon substrates via a sol–gel spin coating method. MOS capacitor were fabricated and characterized with SiO2 and TiO2 as dielectric material on N-type silicon wafer. The thickness was measured by stylus profiler and found to be 510 Å and 528 Å for SiO2 and TiO2 respectively. Some of the material parameters were found from the measured Capacitance -Voltage (C-V) curve obtained by SUPREM-III (Stanford University Process Engineering Model Version 0-83) for SiO2 and C-V Keithly 590 analyzer for TiO2 thin films. The result shows that obtained TiO2 film present a dielectric constant of approximately 80. The refractive index was found to be 2.4 and optical constant was 5.43 obtained from Ellipsometry. Band gap 3.6 eV of TiO2 was calculated by spectrophotometer and Surface morphology was obtained using Scanning Electron Microscope (SEM-JEOL) micrograph. The aluminum (Al) metal was deposited by the thermal evaporation system on the back side of the sample for the ohmic contact. Analysis shows that TiO2 may be acceptable as a viable substitute for high k dielectric in order to prevent the tunneling current problems.
Highlights
The silicon industry has been scaling SiO2 aggressively for low power, high performance CMOS logic applications
Some of the material parameters were found from the measured Capacitance -Voltage (C-V) curve obtained by SUPREM-III (Stanford University Process Engineering Model Version 0-83) for SiO2 and C-V Keithly 590 analyzer for TiO2 thin films
The C-V and I-V results shows that the as deposited TiO2 Nanocrystalline films present a dielectric constant of approximately 73, with good interface quality with silicon and with leakage current density, for 1V of 10 mA/cm2, which may be acceptable for fabricating high performance and low power logic circuits
Summary
The silicon industry has been scaling SiO2 aggressively for low power, high performance CMOS logic applications. The tunneling current increases exponentially as the thickness of the dielectric decreases. A day’s TiO2 oxide layers are being studied intensively as one of the promising high K dielectric for high density DRAM applications [1]. According to International Technology Roadmap for Semiconductor (ITRS) a dielectric constant higher than 25 is needed to meet the scaling goal and at the same time to keep the gate leakage current within tolerable limit (10 A/cm2) [2]. Several high K materials are considered to replace SiO2 gate dielectric among them metal oxides having value high than 25 are of interest [4]. We present the study of Titanium dioxide (TiO2) as a gate dielectric layer
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