Preliminary analysis of RISC architectures performance

Abstract

Analysing architecture performance is a step of utmost importance and interest in the process of computer architecture design. The paper deals particularly with special architectures of the Reduced Instruction Set Computer Space (RISCS) in order to obtain a preliminary evaluation of RISC's architectures performance and the approach to an optimal instruction set for an effective High Level Language Computer (HLLC). The new modular microcomputer consisting of instruction groups modules called MODHEL that has already been proposed has facilitated the investigation of the performance of a set of computers allocated within the RISCS. A comparative study of the dynamic instruction mix of four benchmark programs is performed with respect to the VAX 11/780, RISCI (Berkeley) and five versions of MODHEL. Preliminary results indicate that there is a strong chance that RISC-type computers could be designed to function as efficient low-cost systems.