Prefetching in supercomputer instruction caches

Abstract

Prefetching methods for instruction caches in supercomputers are studied via trace-driven simulation. The two primary methods studied are fall-through prefetch for sequential line accesses and target prefetch for nonsequential ones. As measured by miss rate, both methods are shown to improve performance significantly. When combined in a hybrid algorithm their performance improvement is cumulative. A prefetch efficiency measure that reflects the amount of memory fetch delay that is successfully hidden by prefetching is defined. The better prefetch methods (in terms of miss rate) also have very high efficiencies, hiding approximately 90% of the miss delay for prefetched lines. The results obtained also show that the top-performing prefetch caches produce less memory traffic than the top-performing nonprefetch caches.