Abstract

Spike sorting algorithms is a considerable significant way to collect neural signals in neural signal acquisition systems. One method to realize this function in hardware aspect is to use absolute-value detector. In this paper, the common circuit topology is given by using static CMOS and PTL technology. Then, through comparing with the delay and energy of unit reference inverter, the optimal energy-delay model when sacrificing extra 50% delay can be obtained by the way changing the size of CMOS and Vdd simultaneously, which save nearly 83% energy dissipate than minimal delay model.

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