Abstract
The board level performance of both thermal cycling test and drop test is investigated to ensure good design and robust manufacturing of the WLCSP. The solder joint fatigue life is usually assumed as the judging criterion for the board-level thermal cycling performance of WLCSPs. For the board-level drop test, the solder joints usually fail due to the dynamic impact stress with high strain rate. The investigation of prediction of board-level thermal cycling test and drop test of WLCSPs is performed by FEA modeling. Several fundamental issues of WLCSP are addressed. The concerned issues include: silicon thickness, back side laminate (BSL), PCB with/without buried copper planes, PCB material, and the design rule of depopulated solder array. Simulation results show that the silicon thickness, BSL, and depopulated solder joints of the WLCSP do not have significant impact on the board-level drop test performance. The WLCSP with thinner silicon, no BSL, and with 4 corner solder balls removed, may improve the board-level thermal cycling performance.
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