Abstract
The purpose of this paper is to describe an predictable CPU architecture, based on the five stage pipeline assembly line and a hardware scheduler engine. We aim at developing a fine-grained multithreading implementation, named nMPRA-MT. The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device. An original implementation of a MIPS processor with thread interleaved pipeline is obtained, using dynamic scheduling of hard real-time tasks and interrupts. In terms of interrupts handling, the architecture uses a particular method consisting of assigning interrupts to tasks, which insures an efficient control for both the context switch, and the system real-time behavior. The originality of the approach resides in the predictability and spatial isolation of the hard real-time tasks, executed every two clock cycles. The nMPRA-MT architecture is enabled by an innovative scheme of predictable scheduling algorithm, without stalling the pipeline assembly line.
Highlights
The spectacular development of the embedded systems in the past few years confirm their importance and major impact on the present-day scientific, technological, and socioeconomic areas
If the interrupt is assigned to an HT having the highest priority, the execution starts without affecting the pipeline assembly line
A data hazard which stalls the pipeline is not possible in nMPRA-MT, because the new nHSE does not schedule in a continuous manner the instructions from a particular thread τi
Summary
The spectacular development of the embedded systems in the past few years confirm their importance and major impact on the present-day scientific, technological, and socioeconomic areas Their importance is rendered by the extensive applicability area (including real-time and low-power applications) of the present research in fields like automotive, robotics, and industrial control. The FlexPRET, presented in [8], is a fine-grained multithreaded processor designed for mixed-criticality systems This implementation stalls the pipeline assembly line, when the scheduler executes instructions, every clock cycle, from same thread. Field-programmable gate array (FPGA) devices, with a high capacity of the logic gates and efficient prices [2], represent a hardware support for embedded RTOS For this reason we propose a hardware implementation for RTOS functionalities, using the FPGA systems [6].
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