Precision measurement technique of integrated MOS capacitor mismatching using a simple on-chip circuit

Abstract

A precision measurement technique of the capacitor mismatchings of integrated circuits has been required, that is insensitive to parasitic capacitors on the chip, stray capacitors in measurement circuits, and external noises. A new ac measurement technique is developed here that uses an on-chip source-follower circuit and a simple algorithm. The source-follower circuit lowers the output impedance and thereby excludes the effects of external noises and stray capacitors in measurement circuits. In the present technique, capacitively divided ac voltage after the bandpass filter is measured in two steps by exchanging the terminals of the serial capacitors using external switches. Capacitor mismatching, defined by the relative capacitance tolerance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\Delta C/C</tex> , is derived as the ratio of the difference between the two measured voltages to their average. This derivation significantly reduces errors arising from parasitic capacitors on the chip, the nonlinearity of the source-follower circuit, and the pulse wave that can give the gate bias voltage of the source-follower transistor. The measurement error is estimated to be, in the worst case, 0.1 percent of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\Delta C/C</tex> .