Abstract

Background: Growing wireless communication market is forcing the engineers to design portable and cheaper devices. This could be completed by reducing power consumption and saving battery life. Objective: In this study, a bandpass filter with a central frequency of 80 MHz with the ability to digitally tune the central frequency was designed and simulated. OTA-C blocks (gm-C) were utilized to implement the filter. For this purpose, instead of using a fixed capacitor, we use an array of voltage-variable capacitors that are placed in the form of a capacitor bank. Results: The proposed filter was implemented at the transistor level with 180 nm CMOS technology and simulated with the RF H-spice software. In the proposed filter, the bandwidth of 20 MHz was digitally tuned by 1 MHz increments. The average power consumption at the center frequency of 80 MHz was equal to 24.23 mW. Conclusion: The practical analysis of the digitally tuning filter technique and the simulation results are explained. A comparison of the performance parameters of the simulated filter with state-of-the-art filters indicates that the proposed filter can change its bandwidth over a wide range with the lower power consumption and the lower noise.

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