Abstract
The process integration and other issues associated with lateral and substrate PNP fabrication utilizing the various steps of a contemporary BICMOS process are outlined. The parameters affecting PNP performance examined are photolithographically determined base width, epitaxial silicon thickness and doping, buried layers, the diffusion steps selected for the formation of the emitter/collector, and the CMOS process enhancements. Hot carrier effects are also studied for the PNP devices.
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