Abstract
Power-efficient VLSI realization of decimal convolution algorithms for resource-constrained environments: a design perspective in CMOS and double-gate CMOS technology
Full Text 
Sign-in/Register to access full text options
Sign-in/Register to access full text options 
Published version (
Free)
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
