Power-Efficient Active-RC CT DSM with a Lowpass Capacitor at the Virtual Ground Node of the First Integrator

Abstract

A power-efficient active-RC continuous-time Delta-Sigma modulator (CT-DSM) circuit topology is proposed with a lowpass filter (LPF) capacitor placed at the virtual ground node of the first integrator. A parasitic capacitor always exists at the virtual ground node of an active-RC integrator, generating an unwanted high-frequency pole. With a deliberately added large capacitor at the virtual ground node, the parasitic pole turns into a wanted low-frequency pole for the loop filter of the CT-DSM. Together with its DC pole, the active-RC integrator now realizes two poles for the CT-DSM, reducing amplifiers needed in the modulator. Furthermore, the built-in LPF significantly attenuates and smoothens out the sharp edges of the current to the integrating capacitor, thereby greatly reduces the slew-rate and bandwidth requirements of the crucial first amplifier in the modulator for lower power consumption. A design example for Bluetooth applications is implemented in a 0.18-μm CMOS technology. Simulations show that it achieves 79dB SNDR over 2 MHz bandwidth with 393μW power consumption from 1.8V, which corresponds to a FOM of 13.6 fJ/conv.-step.