Power-delay-area efficient design of vedic multiplier using adaptable manchester carry chain adder

Abstract

Multipliers are basic building blocks for many arithmetic logic units, digital signal processors, coding theory units, communication systems, image processing systems etc. So multipliers designed with high speed and power efficient are essential for high performance processing units. The speed of multiplier is limited by propagation delay of adder. Therefore, design of efficient adders is critical in high performance multipliers. Vedic multipliers is one of the fastest multipliers which are focused recently. In this paper, we propose an power-delay efficient design of Vedic multiplier using adaptable Manchester Carry Chain adders (MCC) in a hierarchal approach. The proposed Vedic multiplier design using MCC is evaluated and analyzed in terms of power, delay and area in a standard 45nm CMOS technology in CADENCE. The proposed Vedic multiplier design using MCC has lower power-delay product requirement than existing Vedic multiplier architectures.