Power-Aware SE Analysis of Different FF Designs at the 14-/16-nm Bulk FinFET CMOS Technology Node

Abstract

As the minimum feature size on an integrated circuit continues to shrink aggressively toward deep submicrometer, the radiation-induced single-event (SE) upset (SEU) has become a prominent concern. Various radiation-hardening-by-design (RHBD) techniques have been developed to achieve a satisfactory SE tolerance for flip-flop (FF) designs. To enable low supply voltage for ICs and overcome the “power wall,” the lowest power consumption of different RHBD techniques to meet the target SEU cross section is studied in this paper. A comparative analysis of three representative RHBD FFs and an unhardened FF fabricated at the 14-/16-nm bulk FinFET CMOS technology generation shows that at least 2× power dissipation reduction may be achieved by using RHBD FFs at appropriate supply voltage without degrading SE tolerance.