Power-aware optimization of software-based self-test for L1 caches in microprocessors

Abstract

In the era of terascale integration, the “reliability wall” and the “power wall” arise as barriers imposing significant challenges to the microprocessor industry. Nowadays, on-line testing is essential for modern microprocessors to detect latent defects that either escaped manufacturing testing or appear during system operation. Moreover, many-core scaling is now facing the “power wall”. More cores can now be placed on a chip than can be concurrently operating due to energy/power limitations. Software-Based Self-Test (SBST) is a flexible and low-cost solution for on-line March test application and defect detection in small memories, such as L1 caches, that lack Memory Built-In Self-Test (MBIST) hardware. In this paper, a power-aware optimization of the SBST methodology introduced in [10] is presented targeting Ll caches by analyzing the unique characteristics of March SBST routines and possible power optimizations without sacrificing March test quality. Experimental results using an architectural-level-power evaluation framework based on GEM5 and McPAT show that the exploitation of Direct Cache Access (DCA) instructions introduced in [10] along with the application of compiler-based power optimizations can achieve significant power savings up to 82.27% and energy savings up to 84,89% for the UltraSPARC Tl processor core. To the best of our knowledge, this is the first paper that addresses power-aware SBST for L1 caches in microprocessors.