Power-Area Trade-Offs in Divided Word Line Memory Arrays

Abstract

Since on-chip caches account for a significant portion of the power budget of modern microprocessors, low power caches are needed in microprocessors destined for portable electronic applications. A significant portion of the power consumption of caches comes from accessing the cache memory array and most of the power consumption of the memory array comes from driving the bit line pairs (i.e., the column current). Various memory array architectures have been proposed to improve the word line delay and the column current. For example, in a divided word line memory array memory cells in each row are organized into blocks. Only the memory cells which are in the activated block have their bit line pairs driven, thus both improving the speed (by decreasing the word line delay) and lowering the power consumption (by decreasing the column current). In this paper we analyze the power-area tradeoffs of divided word line memories with different size blocks. We compare the area and power consumption of 16 Kbit and 64 Kbit memory arrays with 2, 4, 8, and 16 memory cells per block. Our experiments show that a divided word line memory array can lower the power consumption by 50% to 90% over a nondivided word line memory array. However, they consume more area; the area of a divided word line memory array can be 15% to 27% larger than the area of a comparable nondivided word line array. Our experiments also showed that divided word line memory arrays with two or four memory cells in a block have better power-area product than those with more than four cells per block.