Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications

Abstract

This paper proposes a power saving scheme to be used in standard cell based Flash ADC for wireless surveillance applications. The input signal to the wireless surveillance network has a very low activity during night time as compared to day time. Thus, the input signal rarely reaches voltage greater than a reference voltage $$V_Z$$ . The reference voltage $$V_Z$$ can be obtained by collecting a large number of light intensity samples during night time. The proposed power saving scheme uses an auxiliary standard cell comparator, whose switching threshold is kept equal to the reference voltage. The output of the auxiliary comparator disables a large number of comparator for all switching threholds greater than the reference voltage, thereby improving the power efficiency of the ADC. and simulated in a SCL 180 nm CMOS technology with a supply voltage of 1.8 V. The results show that the proposed design achieves an effective number of bits (ENOB) of 4.66 bits. The total power consumption of the proposed architecture using power saving scheme reduces at least by a factor of 2.5 in all the corners when compared to the existing standard cell based Flash ADC without power saving scheme.