Power reduction through X-filling of transition fault test vectors for LOS testing

Abstract

Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) are the two main test schemes for at-speed scan delay testing. In [1, 2], authors proposed a comparison between LOC and LOS, showing that LOS has higher performance than LOC in terms of fault coverage and test length, but higher peak power consumption during the launch-to-capture cycle. This shows the potential benefits of using LOS test scheme provided that power issues can be solved. In this context, this study investigates power reduction of LOS testing through X-filling techniques. Basically, the proposed solution consists in using test relaxation to identify don't-care bits (X-bits) in test vectors and then applying various X-filling techniques so that peak power during the launch-to-capture cycle is comparable to the power consumption in functional mode. In our experiments, we used ITC'99 benchmark circuits synthesized with an industrial 65nm technology. Experimental results show peak power reduction of up to 50% compared to the peak power when test vectors are generated with a conventional ATPG using the random filling option.