Power Profile Obfuscation Using Nanoscale Memristive Devices to Counter DPA Attacks

Abstract

Side channel attacks (SCAs), such as differential power analysis (DPA), are considered as one of the most competent attacks to obtain the secure key of a cryptographic algorithm. Conventional countermeasures for DPAs are focused on hiding and masking techniques at different levels of design abstraction, associated with high power or area cost. However, emerging technologies such as resistive random access memory (RRAM), offer unique opportunities to mitigate SCAs/DPAs with their inherent device characteristics such as variability in write time, ultra low power (0.1-3 pJ/bit), and high density (4F 2). In this research, DPA attacks are mitigated by obfuscating the power profile using inverse RRAM modules. The state memory transaction power traces are balanced when the inverse memory is accessed in tandem with the memory module based on a peripheral balancing logic block. A baseline RTL architecture for the 128-bit AES cryptoprocessor is designed and implemented in CMOS technology. Balancing using RRAM and CMOS memory modules is compared against this baseline architecture. A customized simulation framework is developed for extracting the power traces using Synopsys and Cadence tool suites along with a Hamming weight DPA attack module implemented in Python. The attack mounted on the baseline architectures was successful and the full key was recovered. However, DPA attacks mounted on the inverse CMOS and RRAM-based AES cryptoprocessor yielded unsuccessful results with no keys recovered, demonstrating the resiliency of the proposed architecture against DPA attacks. More importantly, the power consumed with the RRAM balancing logic block is one order lower than the corresponding pure CMOS implementation.