Power modeling and estimation during ADL-driven embedded processor design

Abstract

Rising concern for thermal stress and tight energy constraints have forced designers to consider power as a design criterion from early design phase. Despite many advances in high-level power estimation techniques, there is a lack of generic power estimation capabilities in prominent high-level design flows. In this paper we propose power modeling and estimation techniques during Architecture Description Language (ADL)-based high-level embedded processor design. The first technique is based on accurate switching activity extraction from cycle-accurate instruction-set simulation. The second technique is developed through unit-level power modeling for ADL architecture construct. Multivariate linear regression is used to characterize the unit power model. Experiments are performed on a RISC processor using state-of-the-art high-level processor design flow to demonstrate the accuracy and efficiency of the proposed techniques.