Power Loss Model and Device Sizing Optimization of Si/SiC Hybrid Switches

Abstract

Si/SiC hybrid switches of parallel Si insulated-gate bipolar transistor (IGBT) and SiC metal-oxide-semiconductor field-effect transistor (mosfet) offer most of the SiC benefits but at a much lower cost in comparison to a full SiC solution. The hybrid switch can be optimized to achieve a minimum total power loss while utilizing the smallest SiC chip size without exceeding the specified maximum junction temperature. In this article, we first develop a generalized power loss model for Si/SiC hybrid switches with total power loss and junction temperature as outputs and SiC device size as a continuous input variable, and then develop a methodology to minimize SiC device size while optimizing total IGBT/mosfet power loss and ensuring maximum junction temperature still below 150 °C. The power loss model is experimentally validated through both simple double pulse testing and a dc-dc buck converter case study. Using the model and optimization methodology, a minimum SiC device size can be obtained with optimized power loss and safe operation temperature.